Fujitsu DTV/STB solution driver (FAPex driver) Documentation [V01L00R00]


fapex/sys_config_mb86h61_devkit.h File Reference

Fujitsu DEVKIT specific board configuration for MB86H61. More...

Defines

#define FAPEX_SYS_CLOCK_FREQUENCY   396000000
#define FAPEX_SYS_TIMER_FREQUENCY   99000000
#define FAPEX_SYS_UART_FREQUENCY   99000000
#define DDR_MEMORY_START_1   0x20000000
#define DDR_MEMORY_START_2   0x40000000
#define DDR_MEMORY_BYTES_1   0x04000000
#define DDR_MEMORY_BYTES_2   0x04000000
#define MEMORY_OFFSET_VIDEO   0
#define FAPEX_SYS_MMAP_DDR_START   DDR_MEMORY_START_1
#define FAPEX_SYS_MMAP_DDR2_START   DDR_MEMORY_START_2
#define FAPEX_SYS_MMAP_DDR_BYTES   DDR_MEMORY_BYTES_1
#define FAPEX_SYS_MMAP_DDR2_BYTES   DDR_MEMORY_BYTES_2
#define PROGRAM_MEMORY_START   DDR_MEMORY_START_1
#define FAPEX_SYS_MMAP_ARC_APPLICATION_START   ARC_PROGRAM_LOAD_ADDRESS
#define FAPEX_SYS_MMAP_ARC_APPLICATION_BYTES   0x00400000UL
#define FAPEX_SYS_MMAP_VIDEO_DECODER_START   (PROGRAM_MEMORY_START+0x00400000UL)
#define FAPEX_SYS_MMAP_VIDEO_DECODER_BYTES   0x01100000UL
#define FAPEX_SYS_MMAP_VIDEO_FRAME_START   (FAPEX_SYS_MMAP_DDR2_START + MEMORY_OFFSET_VIDEO)
#define FAPEX_SYS_MMAP_VIDEO_FRAME_SIZE   (0x03400000UL)
#define FAPEX_SYS_MMAP_VIDEO_SCALER_START   (0xFFFFFFFFUL)
#define FAPEX_SYS_MMAP_VIDEO_SCALER_SIZE   (0x00400000UL)
#define FAPEX_SYS_MMAP_BM01_GLOBAL_OFFSET   FAPEX_SYS_MMAP_DDR_START
#define FAPEX_SYS_MMAP_BM23_GLOBAL_OFFSET   FAPEX_SYS_MMAP_DDR_START
#define FAPEX_SYS_MMAP_BM_I2S0_START   (PROGRAM_MEMORY_START+0x01500000UL)
#define FAPEX_SYS_MMAP_BM_I2S0_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_I2S1_START   (PROGRAM_MEMORY_START+0x01510000UL)
#define FAPEX_SYS_MMAP_BM_I2S1_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_I2S2_START   (PROGRAM_MEMORY_START+0x01520000UL)
#define FAPEX_SYS_MMAP_BM_I2S2_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_I2S3_START   (PROGRAM_MEMORY_START+0x01530000UL)
#define FAPEX_SYS_MMAP_BM_I2S3_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_SPDIF_START   (PROGRAM_MEMORY_START+0x01540000UL)
#define FAPEX_SYS_MMAP_BM_SPDIF_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_TELETEXT_START   (PROGRAM_MEMORY_START+0x01550000UL)
#define FAPEX_SYS_MMAP_BM_TELETEXT_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_AUDIO_STREAM_START   (PROGRAM_MEMORY_START+0x01560000UL)
#define FAPEX_SYS_MMAP_BM_AUDIO_STREAM_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_SUBTITLE_START   (PROGRAM_MEMORY_START+0x01570000UL)
#define FAPEX_SYS_MMAP_BM_SUBTITLE_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_AUDIO2_STREAM_START   (PROGRAM_MEMORY_START+0x01580000UL)
#define FAPEX_SYS_MMAP_BM_AUDIO2_STREAM_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_SECTION_START   (PROGRAM_MEMORY_START+0x01590000UL)
#define FAPEX_SYS_MMAP_BM_SECTION_BYTES   0x00100000UL
#define FAPEX_SYS_MMAP_BM_SECTION_END   (FAPEX_SYS_MMAP_BM_SECTION_START+FAPEX_SYS_MMAP_BM_SECTION_BYTES)
#define FAPEX_SYS_MMAP_SPARE_RESERVED_START   (PROGRAM_MEMORY_START+0x01690000UL)
#define FAPEX_SYS_MMAP_SPARE_RESERVED_BYTES   0x00070000UL
#define FAPEX_SYS_MMAP_UNCASHED_HEAP_START   0x21700000UL
#define FAPEX_SYS_MMAP_UNCASHED_HEAP_SIZE   0x00100000UL
#define FAPEX_SYS_MMAP_CURSOR_PLANE_START   0x21800000UL
#define FAPEX_SYS_MMAP_CURSOR_PLANE_BYTES   0x00004000UL
#define FAPEX_SYS_MMAP_OSD_PLANE_START   0x21804000UL
#define FAPEX_SYS_MMAP_OSD_PLANE_BYTES   0x006FC000UL
#define FAPEX_SYS_MMAP_OSD_PLANE_END   0x21F00000UL
#define PROGRAM_LOAD_ADDRESS   0x22000000UL
#define FAPEX_SYS_MMAP_ARM_APPLICATION_START   PROGRAM_LOAD_ADDRESS
#define FAPEX_SYS_MMAP_ARM_APPLICATION_BYTES   0x02000000UL
#define FAPEX_SYS_MMAP_BM_VIDEO_STREAM_START   (FAPEX_SYS_MMAP_VIDEO_DECODER_START + 0x00900000UL)
#define FAPEX_SYS_MMAP_BM_VIDEO_STREAM_BYTES   0x00800000UL
#define FAPEX_SYS_MMAP_OSD_BORDER_MASK   ~(FAPEX_SYS_MMAP_OSD_BORDER_SIZE - 1)
#define FAPI_SYS_INIT_UART   0
#define FAPI_SYS_INIT_TIMER   1
#define FAPI_SYS_INIT_INTR   1
#define FAPI_SYS_INIT_ICC   1
#define FAPI_SYS_INIT_BM   1
#define FAPI_SYS_INIT_FLASH   1
#define FAPI_SYS_INIT_AUOUT   1
#define FAPI_SYS_INIT_VIDEC   1
#define FAPI_SYS_INIT_VISCALE   1
#define FAPICORE_INIT_GPIO   1
#define FAPICORE_INIT_DMA   1
#define FAPICORE_INIT_FPC   1
#define FAPICORE_INIT_UPI   1
#define FAPICORE_INIT_CLKPWR   1
#define FAPICORE_INIT_FLASH   1
#define FAPICORE_INIT_BOOT   1
#define FAPICORE_INIT_GPREG   1
#define FAPICORE_INIT_HDMI   1
#define FAPICORE_INIT_I2C   1
#define FAPICORE_INIT_ICC   1
#define FAPICORE_INIT_INTR   1
#define FAPICORE_INIT_IR   1
#define FAPICORE_INIT_SSP   1
#define FAPICORE_INIT_TIMER   1
#define FAPICORE_INIT_MMU   0
#define FAPICORE_INIT_ETH   0
#define FAPICORE_INIT_UART   0
#define FAPICORE_INIT_USB   0
#define FAPEX_HCB_BLK_I2S   0
#define FAPEX_HCB_BLK_SPDIF   0
#define FAPEX_HCB_BLK_TTX   0
#define FAPEX_HCB_BLK_AUDEC   0
#define FAPEX_HCB_BLK_VIDEC   0
#define FAPI_SYS_UART_SET_BOARD_PARAMS
#define FAPI_SYS_TIMER_SET_BOARD_PARAMS   timer_funcStr.SetClockFrequency( FAPEX_SYS_TIMER_FREQUENCY );
#define FAPI_SYS_INTR_SET_BOARD_PARAMS
#define FAPI_SYS_ICC_SET_BOARD_PARAMS
#define FAPI_SYS_BM_SET_BOARD_PARAMS
#define FAPI_SYS_FLASH_SET_BOARD_PARAMS
#define FAPI_SYS_AUOUT_SET_BOARD_PARAMS
#define FAPI_SYS_VIDEC_SET_BOARD_PARAMS
#define FAPI_SYS_VISCALE_SET_BOARD_PARAMS   viscale_funcStr.PreInit(FAPEX_SYS_MMAP_VIDEO_SCALER_START);

Detailed Description

Fujitsu DEVKIT specific board configuration for MB86H61.

This file contains the settings for the Fujitsu DEVKIT board of MB86H61. It defines all available drivers and their required parameter settings.
In case of Linux environment, this file is included by sys_config.h with configuration of "make menuconfig".
In case of RTOS environment, this file is included by sys_config.h if the following is set within the main configuration file Config.mak:

  • DECODER = MB86H61
  • BOARDNAME = mb86h61_dk01
Attention:
This program is provided as is. You can redistribute it and/or modify it. Fujitsu Semiconductor Limited accepts no responsibility or liability for any errors or omissions.

(C) Copyright 2006-2010 by Fujitsu Semiconductor Europe GmbH
(C) Copyright 2008-2010 by Fujitsu Semiconductor Limited


Define Documentation

#define FAPEX_SYS_CLOCK_FREQUENCY   396000000
#define FAPEX_SYS_TIMER_FREQUENCY   99000000
#define FAPEX_SYS_UART_FREQUENCY   99000000
#define DDR_MEMORY_START_1   0x20000000
#define DDR_MEMORY_START_2   0x40000000
#define DDR_MEMORY_BYTES_1   0x04000000
#define DDR_MEMORY_BYTES_2   0x04000000
#define MEMORY_OFFSET_VIDEO   0
#define FAPEX_SYS_MMAP_DDR_START   DDR_MEMORY_START_1
#define FAPEX_SYS_MMAP_DDR2_START   DDR_MEMORY_START_2
#define FAPEX_SYS_MMAP_DDR_BYTES   DDR_MEMORY_BYTES_1
#define FAPEX_SYS_MMAP_DDR2_BYTES   DDR_MEMORY_BYTES_2
#define PROGRAM_MEMORY_START   DDR_MEMORY_START_1
#define FAPEX_SYS_MMAP_ARC_APPLICATION_START   ARC_PROGRAM_LOAD_ADDRESS
#define FAPEX_SYS_MMAP_ARC_APPLICATION_BYTES   0x00400000UL
#define FAPEX_SYS_MMAP_VIDEO_DECODER_START   (PROGRAM_MEMORY_START+0x00400000UL)
#define FAPEX_SYS_MMAP_VIDEO_DECODER_BYTES   0x01100000UL
#define FAPEX_SYS_MMAP_VIDEO_FRAME_START   (FAPEX_SYS_MMAP_DDR2_START + MEMORY_OFFSET_VIDEO)
#define FAPEX_SYS_MMAP_VIDEO_FRAME_SIZE   (0x03400000UL)
#define FAPEX_SYS_MMAP_VIDEO_SCALER_START   (0xFFFFFFFFUL)
#define FAPEX_SYS_MMAP_VIDEO_SCALER_SIZE   (0x00400000UL)
#define FAPEX_SYS_MMAP_BM01_GLOBAL_OFFSET   FAPEX_SYS_MMAP_DDR_START
#define FAPEX_SYS_MMAP_BM23_GLOBAL_OFFSET   FAPEX_SYS_MMAP_DDR_START
#define FAPEX_SYS_MMAP_BM_I2S0_START   (PROGRAM_MEMORY_START+0x01500000UL)
#define FAPEX_SYS_MMAP_BM_I2S0_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_I2S1_START   (PROGRAM_MEMORY_START+0x01510000UL)
#define FAPEX_SYS_MMAP_BM_I2S1_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_I2S2_START   (PROGRAM_MEMORY_START+0x01520000UL)
#define FAPEX_SYS_MMAP_BM_I2S2_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_I2S3_START   (PROGRAM_MEMORY_START+0x01530000UL)
#define FAPEX_SYS_MMAP_BM_I2S3_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_SPDIF_START   (PROGRAM_MEMORY_START+0x01540000UL)
#define FAPEX_SYS_MMAP_BM_SPDIF_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_TELETEXT_START   (PROGRAM_MEMORY_START+0x01550000UL)
#define FAPEX_SYS_MMAP_BM_TELETEXT_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_AUDIO_STREAM_START   (PROGRAM_MEMORY_START+0x01560000UL)
#define FAPEX_SYS_MMAP_BM_AUDIO_STREAM_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_SUBTITLE_START   (PROGRAM_MEMORY_START+0x01570000UL)
#define FAPEX_SYS_MMAP_BM_SUBTITLE_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_AUDIO2_STREAM_START   (PROGRAM_MEMORY_START+0x01580000UL)
#define FAPEX_SYS_MMAP_BM_AUDIO2_STREAM_BYTES   0x00010000UL
#define FAPEX_SYS_MMAP_BM_SECTION_START   (PROGRAM_MEMORY_START+0x01590000UL)
#define FAPEX_SYS_MMAP_BM_SECTION_BYTES   0x00100000UL
#define FAPEX_SYS_MMAP_BM_SECTION_END   (FAPEX_SYS_MMAP_BM_SECTION_START+FAPEX_SYS_MMAP_BM_SECTION_BYTES)
#define FAPEX_SYS_MMAP_SPARE_RESERVED_START   (PROGRAM_MEMORY_START+0x01690000UL)
#define FAPEX_SYS_MMAP_SPARE_RESERVED_BYTES   0x00070000UL
#define FAPEX_SYS_MMAP_UNCASHED_HEAP_START   0x21700000UL
#define FAPEX_SYS_MMAP_UNCASHED_HEAP_SIZE   0x00100000UL
#define FAPEX_SYS_MMAP_CURSOR_PLANE_START   0x21800000UL
#define FAPEX_SYS_MMAP_CURSOR_PLANE_BYTES   0x00004000UL
#define FAPEX_SYS_MMAP_OSD_PLANE_START   0x21804000UL
#define FAPEX_SYS_MMAP_OSD_PLANE_BYTES   0x006FC000UL
#define FAPEX_SYS_MMAP_OSD_PLANE_END   0x21F00000UL
#define PROGRAM_LOAD_ADDRESS   0x22000000UL
#define FAPEX_SYS_MMAP_ARM_APPLICATION_START   PROGRAM_LOAD_ADDRESS
#define FAPEX_SYS_MMAP_ARM_APPLICATION_BYTES   0x02000000UL
#define FAPEX_SYS_MMAP_BM_VIDEO_STREAM_START   (FAPEX_SYS_MMAP_VIDEO_DECODER_START + 0x00900000UL)
#define FAPEX_SYS_MMAP_BM_VIDEO_STREAM_BYTES   0x00800000UL
#define FAPEX_SYS_MMAP_OSD_BORDER_MASK   ~(FAPEX_SYS_MMAP_OSD_BORDER_SIZE - 1)
#define FAPI_SYS_INIT_UART   0
#define FAPI_SYS_INIT_TIMER   1
#define FAPI_SYS_INIT_INTR   1
#define FAPI_SYS_INIT_ICC   1
#define FAPI_SYS_INIT_BM   1
#define FAPI_SYS_INIT_FLASH   1
#define FAPI_SYS_INIT_AUOUT   1
#define FAPI_SYS_INIT_VIDEC   1
#define FAPI_SYS_INIT_VISCALE   1
#define FAPICORE_INIT_GPIO   1
#define FAPICORE_INIT_DMA   1
#define FAPICORE_INIT_FPC   1
#define FAPICORE_INIT_UPI   1
#define FAPICORE_INIT_CLKPWR   1
#define FAPICORE_INIT_FLASH   1
#define FAPICORE_INIT_BOOT   1
#define FAPICORE_INIT_GPREG   1
#define FAPICORE_INIT_HDMI   1
#define FAPICORE_INIT_I2C   1
#define FAPICORE_INIT_ICC   1
#define FAPICORE_INIT_INTR   1
#define FAPICORE_INIT_IR   1
#define FAPICORE_INIT_SSP   1
#define FAPICORE_INIT_TIMER   1
#define FAPICORE_INIT_MMU   0
#define FAPICORE_INIT_ETH   0
#define FAPICORE_INIT_UART   0
#define FAPICORE_INIT_USB   0
#define FAPEX_HCB_BLK_I2S   0
#define FAPEX_HCB_BLK_SPDIF   0
#define FAPEX_HCB_BLK_TTX   0
#define FAPEX_HCB_BLK_AUDEC   0
#define FAPEX_HCB_BLK_VIDEC   0
#define FAPI_SYS_UART_SET_BOARD_PARAMS
#define FAPI_SYS_TIMER_SET_BOARD_PARAMS   timer_funcStr.SetClockFrequency( FAPEX_SYS_TIMER_FREQUENCY );
#define FAPI_SYS_INTR_SET_BOARD_PARAMS
Value:
intr_funcStr.SetReceiver( FAPI_INTR_TIMER0      , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_TIMER1      , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_TIMER2      , FAPI_INTR_RECEIVER_NONE ); \
            intr_funcStr.SetReceiver( FAPI_INTR_UART        , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_BLTE        , FAPI_INTR_RECEIVER_NONE ); \
            intr_funcStr.SetReceiver( FAPI_INTR_SATA        , FAPI_INTR_RECEIVER_NONE ); \
            intr_funcStr.SetReceiver( FAPI_INTR_SDIO        , FAPI_INTR_RECEIVER_NONE ); \
            intr_funcStr.SetReceiver( FAPI_INTR_SSP         , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_ICC         , FAPI_INTR_RECEIVER_NONE ); \
            intr_funcStr.SetReceiver( FAPI_INTR_FPC_IR      , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_I2C         , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_AMCPU_AXP   , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_GPIO        , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_DMA         , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_HDMAC       , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_USB         , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_ETH         , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_AUDIO       , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_BM          , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_TSD         , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_VO0         , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_VO1         , FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_VO2_HDMI_CEC, FAPI_INTR_RECEIVER_ARM  ); \
            intr_funcStr.SetReceiver( FAPI_INTR_POLLING_MODE, FAPI_INTR_RECEIVER_ARM  );
#define FAPI_SYS_ICC_SET_BOARD_PARAMS
Value:
icc_funcStr.SetClkDivider( FAPI_ICC0, 1 );     \
            icc_funcStr.SetTDA8004TEnable( FAPI_ICC0, 1 );
#define FAPI_SYS_BM_SET_BOARD_PARAMS
Value:
bm_funcStr.SetBufferPurpose(FAPI_BM_I2S0_BUFFER, FAPI_BM0,                                                 \
                                        FAPEX_SYS_MMAP_BM_I2S0_START, FAPEX_SYS_MMAP_BM_I2S0_BYTES);                   \
            bm_funcStr.SetBufferPurpose(FAPI_BM_I2S1_BUFFER, FAPI_BM0,                                                 \
                                        FAPEX_SYS_MMAP_BM_I2S1_START, FAPEX_SYS_MMAP_BM_I2S1_BYTES);                   \
            bm_funcStr.SetBufferPurpose(FAPI_BM_I2S2_BUFFER, FAPI_BM0,                                                 \
                                        FAPEX_SYS_MMAP_BM_I2S2_START, FAPEX_SYS_MMAP_BM_I2S2_BYTES);                   \
            bm_funcStr.SetBufferPurpose(FAPI_BM_I2S3_BUFFER, FAPI_BM0,                                                 \
                                        FAPEX_SYS_MMAP_BM_I2S3_START, FAPEX_SYS_MMAP_BM_I2S3_BYTES);                   \
            bm_funcStr.SetBufferPurpose(FAPI_BM_SPDIF_BUFFER, FAPI_BM0,                                                \
                                        FAPEX_SYS_MMAP_BM_SPDIF_START, FAPEX_SYS_MMAP_BM_SPDIF_BYTES);                 \
            bm_funcStr.SetBufferPurpose(FAPI_BM_TELETEXT_BUFFER, FAPI_BM0,                                             \
                                        FAPEX_SYS_MMAP_BM_TELETEXT_START, FAPEX_SYS_MMAP_BM_TELETEXT_BYTES);           \
            bm_funcStr.SetBufferPurpose(FAPI_BM_AUDIO_STREAM_BUFFER, FAPI_BM0,                                         \
                                        FAPEX_SYS_MMAP_BM_AUDIO_STREAM_START, FAPEX_SYS_MMAP_BM_AUDIO_STREAM_BYTES);   \
            bm_funcStr.SetBufferPurpose(FAPI_BM_SPDIF_STREAM_BUFFER, FAPI_BM0,                                         \
                                        FAPEX_SYS_MMAP_BM_AUDIO2_STREAM_START, FAPEX_SYS_MMAP_BM_AUDIO2_STREAM_BYTES); \
            bm_funcStr.SetBufferPurpose(FAPI_BM_VIDEO_STREAM_BUFFER, FAPI_BM0,                                         \
                                        FAPEX_SYS_MMAP_BM_VIDEO_STREAM_START, FAPEX_SYS_MMAP_BM_VIDEO_STREAM_BYTES);
#define FAPI_SYS_FLASH_SET_BOARD_PARAMS
Value:
flash_funcStr.SetEnable(FAPI_FLASH_DEVICE_PFLASH, 1);   \
            flash_funcStr.SetEnable(FAPI_FLASH_DEVICE_SFLASH, 1);   \
            flash_funcStr.SetUpiIndex(FAPI_FLASH_DEVICE_PFLASH, 0);
#define FAPI_SYS_AUOUT_SET_BOARD_PARAMS
Value:
auout_funcStr.SetSpeakers(FAPI_AUOUT_I2S_0,          \
                                      FAPI_AUOUT_SPEAKER_LEFT,   \
                                      FAPI_AUOUT_SPEAKER_RIGHT); \
            auout_funcStr.SetInternalDac(FAPI_AUOUT_I2S_0);
#define FAPI_SYS_VISCALE_SET_BOARD_PARAMS   viscale_funcStr.PreInit(FAPEX_SYS_MMAP_VIDEO_SCALER_START);


Copyright © 2006-2010 by Fujitsu Semiconductor Europe GmbH
Copyright © 2008-2010 by Fujitsu Semiconductor Limited

Disclaimer:
Please note that the use of this has been based on the terms and conditions of "DK Consent Letter (For Linux)" agreement between you and Fujitsu Semiconductor Limited.
The contents of this document may be revised without prior notice. Contact our sales department for confirmation. The information in this document are presented as is, no license is granted by implication or otherwise.
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